Overview

The convergence of advanced process technology, increasing levels of integration, and higher operating frequencies pose considerable challenges to IP designers whose circuits are required to function in a variety of conditions. One key aspect of the reliable operation of these complex circuits is the quality of the voltage supply they receive. Existing methods do not provide sufficient capabilities to predict the impact of power and ground supply fluctuation on various key circuit parameters, like noise margin, clock jitter, and delays.

Ansys Totem offers a comprehensive co-simulation framework for analog, mixed-signal, and custom circuit designers. It analyzes static (IR, EM) and dynamic noise (DvD1) for the power and ground network at the IP or full-chip level along with the impact of current flow on signal lines (signal EM). Totem provides a comprehensive full-chip solution for modeling and simulating noise injection, propagation, and coupling through the on-die power grid RLC, substrate RC, and package RLC networks.

Features

Integrated Analog and Custom Circuit Simulation Platform

Our layout-based analog and custom circuit simulation platform is ideal for power noise and reliability analyses. Totem uses a single-pass flow that can be applied to early layout connectivity analysis, static voltage drop verification, dynamic power noise sign-off, power/signal net electromigration (EM) analyses, and substrate noise coupling verification. The software displays results in a rich GUI environment; it also generates data reports, maps, and waveforms for debugging.

Connectivity Analysis

Totem’s connectivity checks help you to quickly identify layout issues, such as missing vias, shorts, and unconnected or weakly connected devices. Network topology analysis provides insight into routing issues that might cause voltage drop hot spots or current congestions. You can perform connectivity analysis early in the design stage, soon after the design layout is available ― you don’t need to wait for post-layout signal net extraction and SPICE characterization of device currents.